The subject matter of the present invention relates to circuitry for converting CMOS logic levels to corresponding ECL logic levels to permit the coupling of CMOS circuits to ECL circuits.
To couple a CMOS circuit to an ECL circuit the difference between the output voltages from the one circuit and the input voltages needed by the second circuit must be generated by some form of interfacing circuit. A CMOS circuit's logic level "1" will approach the power supply value, generally 3 volts, while its logic level "0" will be near the reference or ground level. On the other hand, an ECL circuit's logic level "0" will approach -1.8 V, while its logic level "1" will approach -0.88 volts.
Circuitry for performing an interfacing function should contain only a few transistors in order to minimize the use of silicon area and to minimize propagation delays through the transistors.
A patent of interest is U.S. Pat. No. 4,486,671, entitled "Voltage Level Shifting Circuit", by Daniel Ong. The circuit described in that patent is a voltage level shifting circuit that is suitable as an interface circuit between TTL and CMOS circuitry.
Another patent of interest is U.S. Pat. No. 4,486,670, entitled "Monolithic CMOS Low Power Digital Level Shifter", by Yiu-Fai Chan et al. The circuit of that patent provides a power level shift which converts the typical transistor logic levels, for example, typically 5 volts, to a higher voltage, approximately 20 volts, in order to program an EPROM.
Another patent of interest is U.S. Pat. No. 4,453,095, entitled "ECL MOS Buffer Circuits", by R. S. Wrathall. The circuit of that patent is a buffer circuit for interfacing CMOS circuitry with associated ECL devices.